Careers
Build the silicon that powers AI
We are a small team in Bengaluru designing AI processors, die-to-die interconnect chips, and security chips. Every engineer here owns real blocks on real tape-outs.
Open positions
Current openings
All roles are on-site at our Bengaluru office. Open a role to see what the work involves, then apply by email with your CV.
Design Verification Engineer — UCIe
Design Verification Engineer — UCIe
Verify our UCIe die-to-die controller and adapter, from link training through the protocol layers, and sign off the blocks that go to tape-out.
What you will do
- Build and own UVM environments for the UCIe adapter, link training, and sideband
- Write test plans, functional coverage, and assertions from the specification
- Drive regressions to coverage closure and debug failures with designers
- Bring up PCIe and CXL traffic over the die-to-die link
What you bring
- 3+ years of SystemVerilog and UVM verification
- Experience with a serial or die-to-die protocol: UCIe, PCIe, CXL, or Ethernet
- Comfort with SVA, coverage closure, and regression scripting
- Nice to have: UCIe specification or formal verification experience
RTL Design Engineer — Die-to-die interconnect
RTL Design Engineer — Die-to-die interconnect
Design the controller and adapter logic that moves data between dies at high bandwidth and low power.
What you will do
- Write micro-architecture specifications and synthesisable RTL
- Design link-layer logic: retry, CRC, flow control, and clock-domain crossings
- Close timing, area, and power with the implementation team
- Run lint and CDC checks and support verification through sign-off
What you bring
- 4+ years of RTL design in Verilog or SystemVerilog
- Experience with high-speed interface controllers (PCIe, CXL, UCIe, or DDR)
- Working knowledge of synthesis, STA, lint, and CDC tools
- Nice to have: chiplet or multi-die system experience
AI Accelerator Architect
AI Accelerator Architect
Define the compute, memory, and dataflow architecture of our AI processor, working from real model workloads.
What you will do
- Profile training and inference workloads and turn them into architecture requirements
- Build performance and power models to compare design options
- Specify compute arrays, on-chip memory, and the network-on-chip
- Work with RTL and compiler engineers from specification to silicon
What you bring
- 6+ years in processor, GPU, or accelerator architecture
- Strong grasp of neural-network operators, numerics, and memory hierarchies
- Performance modelling in C++ or Python
- Nice to have: shipped an accelerator or worked on an ML compiler
Hardware Security Engineer
Hardware Security Engineer
Design the root of trust and cryptographic blocks in our data-centre security chips, and protect them against physical and logical attacks.
What you will do
- Design secure boot, key storage, and attestation hardware
- Implement and integrate cryptographic engines (AES, SHA, ECC, post-quantum)
- Threat-model designs and add countermeasures against side-channel and fault attacks
- Support security certification and review
What you bring
- 4+ years in hardware security or cryptographic RTL
- Knowledge of roots of trust, secure boot, and key management
- Familiarity with side-channel and fault-injection countermeasures
- Nice to have: Caliptra, OpenTitan, or FIPS 140-3 experience
Physical Design Engineer
Physical Design Engineer
Take blocks from netlist to GDS in advanced nodes and close timing, power, and physical verification for tape-out.
What you will do
- Own floorplanning, placement, clock-tree synthesis, and routing for complex blocks
- Close timing across corners and handle ECOs
- Run power, IR-drop, and electromigration analysis
- Clean DRC and LVS for sign-off
What you bring
- 3+ years of block-level physical design in 7 nm or below
- Hands-on experience with industry place-and-route and STA tools
- Scripting in Tcl and Python
- Nice to have: high-speed I/O or multi-die package experience
Design-for-Test Engineer
Design-for-Test Engineer
Make our chips testable, from scan and memory BIST in each die to test access across multi-die packages.
What you will do
- Plan and insert scan, compression, and memory BIST
- Generate ATPG patterns and drive test-coverage targets
- Build die-to-die and package-level test access (IEEE 1838, 1500)
- Support silicon bring-up and production test
What you bring
- 3+ years of DFT implementation
- Experience with scan insertion, ATPG, and MBIST flows
- Gate-level simulation and pattern debug
- Nice to have: 2.5D or 3D multi-die test experience
VLSI Intern — Design and verification
VLSI Intern — Design and verification
Work alongside our design and verification engineers on real blocks, with a path to a full-time role.
What you will do
- Write RTL or testbench components for a block on a live project
- Run simulations and regressions, and debug failures
- Automate flows with Python and shell scripts
- Present your work to the team at the end of the internship
What you bring
- Final-year B.Tech/B.E. or M.Tech in ECE, EEE, or a related field
- Digital design fundamentals and some Verilog or SystemVerilog
- A project you can walk us through, in coursework or on your own
- Nice to have: UVM, computer architecture, or FPGA experience
No open roles in this team right now. You can still send us a general application below.
General application
Don’t see your role?
If you want to work on AI silicon and your skills fit somewhere in the stack, send us your CV and a short note on what you would like to build.
- Apply tocontact@arqonixgen.com
- IncludeYour CV and the role title in the subject line
- LocationOn-site, Bengaluru, Karnataka